CMPEN 270 Laboratory 5 


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CMPEN 270 Laboratory 5

In this lab you will learn:
1. Timing Hazards in a combinational circuit
2. Finding the consensus term to fix the timing hazard
Timing Hazards in Combinational Circuits
In digital logic, a hazard in a system is an undesirable effect caused by either a deficiency in the system or
external influences. Logic hazards are manifestations of a problem in which changes in the input variables
do not change the output correctly due to some form of delay caused by logic elements (NOT, AND, OR
gates, etc.) This results in the logic not performing its function properly. The three different most common
kinds of hazards are usually referred to as static, dynamic and function hazards. The topic of interest in
today’s lab is static hazard. A static hazard is the situation where, when one input variable changes, the
output changes momentarily before stabilizing to the correct value. There are two types of static hazards
as shown in the figure below:
• Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily
changes to 1,0 before settling on 0
• Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily
changes to 0,1 before settling on 1
One example of a logic where a static-1 hazard can occur is F = XZ’+YZ. Shown below is the logic diagram
and a timing diagram illustrating the occurrence of the hazard in the above function.
CMPEN 270 Laboratory 5 2020
Activity 1: Design Problem
Design a circuit whose input is a 4-bit number (A1 A2 A3 A4) which consists of a CONTROL bit(A1) and three
INPUT bits (A2 A3 A4). The circuit acts as a 1-bit comparator that checks if any two of the three input bits are
equal to “0” depending on the control bit. If the control bit(A1) is “0”, the one bit-comparator outputs(Z) a
HIGH (“1”) value if both bits A3 and A4 are equal to zero. Similarly, If the control bit (A1) is “1”, the one bitcomparator outputs (Z) a HIGH (“1”) value if both bits A2 and A3 are equal to zero.
The functionality of the circuit is as follows:
CMPEN 270 Laboratory 5 2020
Submission Requirements
Please submit everything into 1 file!
Your submission should include:
– 1 filled out truth table
– 1 filled out minimal SOP K-Map
– Minimal SOP circuit expression
– Hazard pair and consensus term
– Screenshot of the final circuit

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