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# Digital Circuit Design HOMEWORK # 5

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ECE 2029 Introduction to Digital Circuit Design
HOMEWORK # 5

ECE Box#:
1) /5
2) /20
3) /10
4) /20
5) /10
6) /15
7) /20
Total /100
TA’s/Instructor’s Signature: _________________________ Date: ___________________
Important (TIPS)
1. Show all the process work neatly, don’t just jump to answer. Partial credit may be given.
2. Read the problem carefully, don’t assume. Look for the simple, straightforward way to solve the
problem. Don’t overdo yourself.
4. If you need to use an extra piece of paper, please staple it on and number your solutions just
like below!
Please turn it into the ECE2029 box located at the ECE department office AK202 above the shelf just
when you walk-in.
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Problem 1 – 5 points total
a) My TV remote has a single MENU button that cycles between 6 different menus that make
adjustments to the picture and sound. When I press the MENU button I go the color balance settings,
then if I hit the button again I go to the brightness. I must then press the button again to get to get to
the sound settings, etc. Finally after pressing the MENU button to enter language settings if I press
or sequential logic? Explain.
b) A household alarm systems has 4 motion sensors (1 per room) and a single system enable or
arming switch by the door. If the system is armed (enabled) and any of the motion sensors is
activated (i.e. is logic 1) then the alarm sounds. If the system is not enabled then the alarm will not
sound whether the motions sensors are activated or not. Is this home security system employing
combinational or sequential logic? Explain.
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Problem 2 – 20 points total
a) Draw the gate-level schematic diagram only for a simple S-R latch, for an S-R Latch with Enable
(CE) and for a D-latch with Enable (CE) – 5 pts
S-R Latch
S-R Latch with Enable (CE)
D-Latch with Enable (C)
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b) Also, fill in the function (or truth) tables for each – 15 pts
S-R Latch
S R Q Q’
S-R Latch with Enable (CE)
CE S R Q Q’
D-Latch with Enable (CE)
CE D Q Q’
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Problem 3- 10 points total
Trace the behavior of a level-sensitive SR latch for the input pattern in the figure below. Assume S1, R1,
and Q are initially 0. Complete the timing diagram, assuming the logic gates have a tiny but non-zero
delay.

S1 …………………………………………………………………………………………………
R1 ……………………………………………………………………………………………………

Q …………………………………………………………………………………………………
CE S R S1 R1 Q Qn (Q-NOT)
CE
CE
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Problem 4 – 20 points total
Analyze the FlightAttendant Call Button using D-Flip Flop as shown below, bottom right:
(Complete all steps.Assume that a button press is logic 1 and not pressed is logic 0)
1) Draw the circuit (including D FF as shown in figure) and identify Next State logic, State Memory
and Output logic blocks – 5 pts
2) Write expressions for Next State and Output logic – 5 pts
3) Fill in the a transition table (shown below) – 5 pts
Call Cancel Q D
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4) Assume some little kid is pressing the buttons. Finish timing diagram (below) ignoring propagation
delays – 5 pts (Assume Blue Light, B.L. = 0 initially)
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Problem 5 – 10 points total
Edge- Triggered D Flip-Flop using a Master Servant Design.
A D flip flop implementing an edge triggered bit storage block, internally using two D-latches as shown
below, explain the working of the flip flop in master servant arrangement and complete the timing
diagram (ignore any propagation delays).
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Problem 6 -15 points total
For the sequential machine in the circuit diagram:
D
CLK
Q
Q D
CLK
Q
Q
X
CLK
F
D1 D0 Q0 Q1
Q’1 Q’0
a) Determine Boolean expressions for next state logic and output logic from the circuit. That is,
express D1, D0 and F as logic expressions in terms of Q1, Q0 and X.
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b) Fill in the state table, given below.
Present State Input Next State Output
Q1 Q0 X Q1
+
Q0
+ F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
c) Draw a state transition diagram for this sequential machine.
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Problem 7 -20 points total
The following sequential circuit is a Pulse Distributor:
Figure 1
Notice: This sequential circuit does not have the input signal and the output Z is the present state of D
flip-flop. The initial condition of output is set as 000.
a) Determine Boolean expressions for next state logic and output logic from the circuit. That is,
express D2, D1, D0 and Z2, Z1, Z0 as logic expressions in terms of Q2, Q1 and Q0. (do not write D
logic expression in terms of Z since Z is the output)
b) Fill in the state table, given below.
Present State(Output) Next State
Q2 Q1 Q0 Q2
+
Q1
+
Q0
+
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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c) Draw a state transition diagram for this sequential machine and timing diagram with CLK, Z0, Z1, and
Z2.
d) From the timing diagram, what the function of this sequential circuit.

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