# Digital Design 1 Lab 3

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CSCE 2302 – Digital Design 1
Lab 3
Decoders and Multiplexers
Objectives
➢ To familiarize students with the structure and the operation of both Multiplexer and Decoder
➢ To implement 2X4 Decoder using NAND gates
➢ To implement 4×1 Mux using NAND gates
➢ To implement Logic Functions using binary Decoder
➢ To implement Logic Functions using Multiplexer
Material
➢ 74HC32 (Quad 2-input OR) or 74HC08 (Quad 2-input AND), to achieve minimum number of chips
➢ 74HC138 (3×8 Decoder)
➢ 74HC151 (8×1 Multiplexer)
➢ Digital Logic Trainer
➢ Wires
Introduction
a. Decoders
A decoder is a logic circuit that detects the precedence of unique input states and generates a unique
output for that state. An example is the binary decoder. A binary decoder has n inputs and 𝟐
𝒏 unique
output lines. Figure 1 shows the circuit diagram for 2×4 binary decoder. Please note that when the input
‘En’ is set to ‘0’, all the outputs y0-y3 will be to ‘0’. When En=1 the decoder operates normally. In normal
mode, every decoder output (y0-y3) is set to 0 except for the one output whose number is input on w1
and w0. For example, if w1w0 = 00, y0 will be set to 1 and all other outputs are set to 0. If w1w0 = 01, y1
will be set to 1 and all other outputs are set to 0. And so on.
Figure 1. The circuit diagram for 2×4 binary decoder with enable
CSCE 2302 – Digital Design 1 Lab Fall 2023
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The circuit can be designed using NAND gates instead of AND gates. In this case every output (y0-y3) is
set to logic ‘1’ except of one output, which is determined by the inputs w0 and w1. A binary decoder is
also called a min/maxterm generator. A minterm generator is constructed using AND and NOT gates.
The appropriate output is indicated by logic 1 (positive logic). A maxterm generator is constructed using
NAND gates. The appropriate output is indicated by logic 0 (Negative logic).
Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single nto-2
n decoder to generate the minterms, and an OR gate to form the sum. Figure 2 shows how to
implement the function (𝑎, 𝑏, 𝑐) = (4, 6, 7) using a 3×8 decoder.
Figure 2. Implementation of function F = ∑𝑚 (4, 6, 7) using a 3×8 decoder
b. Multiplexers
A multiplexer (MUX) is a digital switch, which connects data from one of n sources to the output. A
number of select inputs determine which data source is connected to the output. The MUX acts like a
digitally controlled multi-position switch where the binary code applied to the select inputs controls
the input source that will be switched on to the output. Figure 3 shows the logic circuit and the block
diagram of 4×1 multiplexer.
Figure 3. The logic circuit and the block diagram of 4×1 multiplexer
3×8 Decoder
W0
W1
W2 a
b
c y0
y1
y2
y3
y4
y5
y6
y7 Enable
Logic 1 F
CSCE 2302 – Digital Design 1 Lab Fall 2023
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While Multiplexers are primarily thought of as “data selectors” because they select one of several inputs
to be logically connected to the output, they can also be used to implement Boolean functions. We can
implement any Boolean function of x variables using a 𝟐
𝒙
input MUX. Multiplexers can be used more
effectively by using some forms of functional decomposition; meaning we can implement a 4-variable
function using 8-to-1 MUX by using three of the variables as select inputs and feeding an appropriate
function of the fourth variable to the data inputs of the MUX. Figure 4 shows how this can be done for
the function F (𝑎, 𝑏, 𝑐) = (3, 5, 6, 7).
Figure 4. Implementing a 3-variable function using 4×1 multiplexer
Pre-lab Questions
1. Design a logic circuit that has 3 inputs x2, x1 & x0(x2 is the MSB and x0 is LSB) and two
outputs Y1 & Y2. Y1 indicates whether the 3-bit input (x2 x1 x0) is an odd number, and Y2
is a majority indicator that outputs 1 if the 3-bit input has more ones in it than zeroes.
a. Write the truth table.
b. Get a simplified Boolean equation for Y1 and Y2 using K-maps.
2. Draw the logic circuit diagram for a 2×1 multiplexer implemented using NAND gates only. The
multiplexer inputs are a and b, and the selection line is s. Do not include the multiplexer enable
input.
3. Implement F(x3, x2, x1, x0) = ∑m(1,2,3,6,8,9,12,15) using an 8×1 Multiplexer and inverters if
needed. Connect x3, x2, x1 to the multiplexer selection lines.
Experiments
1. Implementing Logic functions using Decoders:
chip pins correctly.
b. Implement Y1 and Y2 (from pre-lab Q1) using 3×8 Decoder chip(s) and AND gates only
(Remember: the active low decoder can be considered a maxterm generator).
c. Connect the circuit inputs x2, x1, x0 to toggle switches and Y1 and Y2 outputs to LEDs,
d. Use the minimum possible number of chips. How many chips are needed for the whole
circuit and of what type? Include your answer in the lab report.
CSCE 2302 – Digital Design 1 Lab Fall 2023
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2. Building a 2×1 multiplexer using NAND gates:
a. Implement a 2×1 multiplexer using NAND gate chips only (from pre-lab Q2). Connect inputs
a, b, and s to toggle switches and connect the output to one of the LEDs. Record the output
in Table 1 in the lab report.
b. How many chips are used and of what type? Include your answer in the lab report.
3. Implementing Logic functions using Multiplexers:
the chip pins correctly.
b. Implement F(x3, x2, x1, x0) = ∑m(1,2,3,6,8,9,12,15) (from pre-lab Q3) using 74HC151 8×1
Multiplexer chip(s) and 74HC04 inverter chip(s) if needed. Connect x3, x2, x1 to the
multiplexer selection lines.
c. Connect the circuit inputs x3, x2, x1, x0 to toggle switches and F output to LED, then test
d. Use the minimum possible number of chips. How many chips are needed and of what type?
______________________________________________________________________________
CSCE 2302 – Digital Design 1 Lab Fall 2023
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Lab Report [10 Pts]
(Deadline: Tuesday of next week 2:00pm) (Individual submission)
1. [1 Pts] Record the values from experiment 2 in table 1 below and answer the following
questions.
Table 1
Inputs Output
a b s
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
a. How many chips are used in Experiment1(d) and of what type?
b. How many chips are used in Experiment2(b) and of what type?
c. How many chips are used in Experiment3(d) and of what type?
2. [3 Pts] Show how to build a 4×16 decoder using 2×4 decoders
a. Draw the logic diagram.
b. Simulate the circuit on Logisim using 7400 chips only. Double click on the chip on Logisim to
see the internal design.
c. Have a screenshot of the circuit and attach your Logisim .circ file to the report.
3. [6 Pts] Research questions:
a. List 2 known applications that use multiplexers in their circuits, describing its role in each.
b. List 2 known applications that use decoders in their circuits, describing its role in each.
c. Why do some chip designs use active low signals instead of active high?

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