Lab 1 Calculator



ELEC 326 Lab 1
Learn and work in Vivado and design a simple calculator in Verilog. Learn how FPGA programming works
and how to interact with Input and Output pins through the development board.
Inputs to the Calculator
CLK – the onboard 50Mhz clock
o This is needed for the 7—segment display, but will already be hooked up correctly in
the provided Verilog
SW[7:0] – the eight board switches
BTN[3:0] –four board push buttons
Outputs of the Calculator
LED[7:0] – the eight board LEDs
SEG[6:0], DP, AN[3:0] – the seven segment display
o These will already be connected in the provided Verilog
Step 0: Nexys 4 DDR
Download and read the Nexys 4 DDRReference Manual from FPGA Labs section on the course Canvas
page. Read closely chapter 10 on I/O and how Seven Segment Displays work. Describe your understanding
as part of your lab report.
Step 1: Provided files
Download lab1.v and Nexys4DDR_Master.xdc from the course webpage.
Step 2: Seven Segment Display
In lab1.v, implement the segmentFormatter module.
The seven-segment display is implemented with two Verilog modules in the provided file:
module sevenSegDisplay
o This module is completed, and does not require any editing. It contains the sequential logic
for switching between the four digits of the seven-segment display.
module segmentFormatter
o This module is currently empty, and will need to be completed.
o input [3:0] num_pi
§§ A four bit number to be displayed
o output [6:0]


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