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Lab Assignment 4 ECSE104L

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Lab Assignment 4
ECSE104L
Example of Hierarchical Designing in Verilog: –
Full adder Boolean expressionVerilog code for Half Adder
Half Adder:
//Declare the ports of Half adder module
module half_adder(
Data_in_A,
Data_in_B,
Data_out_Sum,
Data_out_Carry
);
//what are the input ports.
input Data_in_A;
input Data_in_B;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;
//Implement the Sum and Carry equations using Verilog Bit operators.
assign Data_out_Sum = Data_in_A ^ Data_in_B; //XOR operation
assign Data_out_Carry = Data_in_A & Data_in_B; //AND operation

endmodule
Verilog code for full adder-
//declare the Full adder verilog module.
module full_adder(
Data_in_A, //input A
Data_in_B, //input B
Data_in_C, //input C
Data_out_Sum,
Data_out_Carry
);
//what are the input ports.
input Data_in_A;
input Data_in_B;
input Data_in_C;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;
//Internal variables
wire ha1_sum;
wire ha2_sum;
wire ha1_carry;
wire ha2_carry;
wire Data_out_Sum;
wire Data_out_Carry;
//Instantiate the half adder 1
half_adder ha1(
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.Data_out_Sum(ha1_sum),
.Data_out_Carry(ha1_carry)
);

//Instantiate the half adder 2
half_adder ha2(
.Data_in_A(Data_in_C),
.Data_in_B(ha1_sum),
.Data_out_Sum(ha2_sum),
.Data_out_Carry(ha2_carry)
);
//sum output from 2nd half adder is connected to full adder output
assign Data_out_Sum = ha2_sum;
//The carry’s from both the half adders are OR’ed to get the final
carry./
assign Data_out_Carry = ha1_carry | ha2_carry;

endmodule
Ques 1 Write Verilog code for half adder. Test using university wave form.
Ques 2. Design a four-bit combinational circuit 2’s complementor using exclusive-OR gates and half
adder. Write Verilog code in Quartus tool then test using university waveform.
Ques 3. Write Verilog code for full adder. Test using university wave form.
Ques 4. Write Verilog code for 4-bit ripple carry adder using full adder. Test using university wave form.

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