Lab Assignment 6 ECSE104L

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Lab Assignment 6
Ques 1 – Document for Test bench tutorial is added along with assignment first go through with all
the steps given in document create MUX design and test bench for mux (given in document ).
Ques 2. Design 4 bit adder and subtractor in same unit where operation choice will control by a
control bit. Verify using Verilog test bench.


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