Ve311 Lab #3
Note:
(1) Please use A4 size papers.
(2) The lab report should be submitted online individually.
(3) Use Proteus 8.10 for simulation before the lab session. In the Proteus
library, you should be able to find all the components used in the schematics.
The lab report must include both the simulation and measurement
results.
1. [Common-Source with Source Degeneration Amplifier]
(a) [20%] (RL = ∞) Design and build a common-source with source
degeneration amplifier, which has a voltage gain Aυ > 5 , using
NMOS (VN0104). Plot VOUT vs VIN. Is the voltage gain Aυ close to
RD⁄RS? (Hint: First choose appropriate 𝑅𝐷 and 𝑅𝑆
. Second, perform
DC sweep to find out a 𝑉𝐼𝑁 at which the magnitude of slope is more
than 5. At the same time, make sure the NMOS is in the saturation
region. If not, change for another 𝑅𝐷 and 𝑅𝑆
, and repeat the DC
sweep again.)
(b) [15%] ( RL = ∞ ) For Vin = VIN + 0.01sin(2π102
∙ time) , plot
Vout = VOUT + υout vs time. Confirm that the amplitude of υout is
equal to 0.01 × Aυ.
(c) [15%] (RL = 50 kΩ) For Vin = VIN + 0.01sin(2π102
∙ time) , plot
Vout = VOUT + υout vs time. Does the amplitude of υout become
smaller than 0.01 × Aυ? If so, explain the reasons. (Note: Make sure
the NMOS remains in the saturation region.)
2
3
2. [Source Follower]
(a) [20%] (RL = ∞) Design and build a source follower, which has a
voltage gain Aυ > 0.5, using NMOS (VN0104). Plot VOUT vs VIN. Is
the voltage gain Aυ close to unity? (Hint: First choose appropriate
𝑅𝑆
. Second, perform DC sweep to find out a 𝑉𝐼𝑁 at which the
magnitude of slope is more than 0.5. Here the NMOS is always in the
saturation region.)
(b) [15%] ( RL = ∞ ) For Vin = VIN + 0.05sin(2π102
∙ time) , plot
Vout = VOUT + υout vs time. Confirm that the amplitude of υout is
equal to 0.05 × Aυ.
(c) [15%] (RL = 50 kΩ) For Vin = VIN + 0.05sin(2π102
∙ time) , plot
Vout = VOUT + υout vs time. Does the amplitude of υout still
maintain around 0.05 × Aυ? If so, explain the reasons.
Supertex inc.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
VN0104
Features
► Free from secondary breakdown
► Low power drive requirement
► Ease of paralleling
► Low CISS and fast switching speeds
► Excellent thermal stability
► Integral source-drain diode
► High input impedance and high gain
Applications
► Motor controls
► Converters
► Amplifiers
► Switches
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
General Description
This enhancement-mode (normally-off) transistor utilizes a
vertical DMOS structure and Supertex’s well-proven, silicongate manufacturing process. This combination produces a
device with the power handling capabilities of bipolar transistors
and the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
N-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Ordering Information
Device
Package Option Wafer / Die Options
TO-92 NW
(Die in wafer form)
NJ
(Die on adhesive tape)
ND
(Die in waffle pack)
VN0104 VN0104N3-G VN1504NW VN1504NJ VN1504ND
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF15 for layout and dimensions.
Pin Configuration
TO-92 (N3)
GATE
SOURCE
DRAIN
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiVN
0 104
YYWW
TO-92 (N3)
Product Marking
Package may or may not include the following marks: Si or
Product Summary
BVDSS/BVDGS
(V)
RDS(ON)
(max)
(Ω)
I
D(ON)
(min)
(A)
40 3.0 2.0
2
VN0104
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
Notes:
† ID (continuous) is limited by max rated Tj
.
Thermal Characteristics
Package
I
D
(continuous)†
(mA)
I
D
(pulsed)
(A)
Power Dissipation
@TC = 25OC
(W)
θjc
(OC/W)
θja
(OC/W)
I
DR
†
(mA)
I
DRM
(A)
TO-92 350 2.0 1.0 125 170 350 2.0
Switching Waveforms and Test Circuit
90%
10%
90% 90%
10% 10%
Pulse
Generator
VDD
RL
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF) t
r
INPUT
INPUT
OUTPUT
10V
VDD
RGEN
0V
0V
t
f
BVDSS Drain-to-source breakdown voltage 40 – – V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage 0.8 – 2.4 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature – -3.8 -5.5 mV/OC VGS = VDS, ID= 1.0mA
I
GSS Gate body leakage – – 100 nA VGS = ± 20V, VDS = 0V
I
DSS Zero gate voltage drain current
– – 1.0
µA
VGS = 0V, VDS = Max Rating
– – 100 VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
I
D(ON) On-state drain current
0.5 1.0 – A
VGS = 5.0V, VDS = 25V
2.0 2.5 – VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance – 3.0 5.0
Ω
VGS = 5.0V, ID = 250mA
– 2.5 3.0 VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature – 0.70 1.0 %/OC VGS = 10V, ID = 1.0A
GFS Forward transductance 300 450 – mmho VDS = 25V, ID = 500mA
CISS Input capacitance – 55 65
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance – 20 25
CRSS Reverse transfer capacitance – 5.0 8.0
t
d(ON) Turn-on delay time – 3.0 5.0
ns
VDD = 25V,
I
D = 1.0A,
RGEN = 25Ω
t
r Rise time – 5.0 8.0
t
d(OFF) Turn-off delay time – 6.0 9.0
t
f Fall time – 5.0 8.0
VSD Diode forward voltage drop – 1.2 1.8 V VGS = 0V, ISD = 1.0A
t
rr Reverse recovery time – 400 – ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
3
VN0104
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves
Thermal Response Characteristics
Thermal Resistance (normalized)
t
P (seconds)
1.0
0.8
0.6
0.4
0.2
0
TO-92
PD = 1.0W
TC = 25OC
0.001 0.01 0.1 1.0 10
Output Characteristics
VDS (volts)
ID (amperes)
0 10 20 30 40
2.5
2.0
1.5
1.0
0.5
0
VGS = 10V
8.0V
6.0V
4.0V
Saturation Characteristics
VDS (volts)
0 2.0 4.0 6.0 8.0 10
2.5
2.0
1.5
1.0
0.5
0
ID (amperes)
Transconductance vs. Drain Current
GFS (siemens)
I
D (amperes)
1.0
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0
VDS = 25V
TA = -55OC
25OC
125OC
Power Dissipation vs. Case Temperature
TC (
OC)
PD (watts)
2.0
1.0
0
0 25 50 75 100 125 150
TO-92
Maximum Rated Safe Operating Area
VDS (volts)
ID (amperes)
0.1 1.0 10 100
10
1.0
0.1
0.01
TO-92 (DC)
TC = 25OC
3.0V
5.0V
7.0V
9.0V
VGS = 10V
8.0V
6.0V
4.0V
3.0V
5.0V
7.0V
9.0V
4
VN0104
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves (cont.)
Gate Drive Dynamic Characteristics
QG (nanocoulombs)
VGS (volts) 10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0
VDS = 10V
40 pF
40V
80 pF
-50 0 50 100 150
1.1
1.0
0.9
BVDSS Variation with Temperature
BVDSS (normalized)
Tj (
OC)
On-Resistance vs. Drain Current
RDS(ON) (Ω)
I
D (amperes)
0 0.5 1.0 1.5 2.0 2.5
5.0
4.0
3.0
2.0
1.0
0
VGS = 5.0V
VGS = 10V
Transfer Characteristics
VGS (volts)
I
D (amperes)
0 2 4 6 8 10
2.5
2.0
1.5
1.0
0.5
0
TA = -55OC
25OC
VDS = 25V
125OC
VGS(th) (normalized)
RDS(ON) (normalized)
V(th) and RDS Variation with Temperature 1.6
1.4
1.2
1.0
0.8
0.6-50 0 50 100 150
V(th)@ 1.0mA
RDS@ 10V, 1.0A
1.9
1.6
1.3
1.0
0.7
0.4
Tj (
OC)
RDS@ 5.0V, 0.25A
Capacitance vs. Drain-to-Source Voltage 100
75
50
25
0
C (picofarads)
0 10 20 30 40
f = 1.0MHz
CISS
COSS
CRSS
VDS (volts)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
5
VN0104
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-VN0104
B071411
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014† .014† .175 .125 .080 .095 .045 .500
NOM – – – – – – – – –
MAX .210 .022† .022† .205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
Seating
Plane
1
2
3
Front View Side View
Bottom View
E1
E
D
e1
L
e
c
1 2 3
b
A
Mouser Electronics
Authorized Distributor
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Microchip:
VN0104N3-P014-G VN0104N3-P014 VN0104N3-P013 VN0104N3-P003 VN0104N3-P002 VN0104N3-G
VN0104N3 VN0104N3-P013-G VN0104N3-P002-G VN0104N3-P003-G VN0104N3-G P002 VN0104N3-G P013
VN0104N3-G P005 VN0104N3-G P003 VN0104N3-G P014 VN0104N3-G-P013
