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# Digital Circuit Design HOMEWORK # 3

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1
ECE 2029 Introduction to Digital Circuit Design
HOMEWORK # 3

Problems Score Instructor/TA’s Comments
1) /35
2) /20
3) /45
Total /100
TA’s/Instructor’s Signature: _________________________ Date: ___________________
Important (TIPS)
1. Show all the process work neatly, don’t just jump to answer. Partial credit may be given.
2. Read the problem carefully, don’t assume. Look for the simple, straightforward way to solve
the problem. Don’t overdo yourself.
3. To make the grading easier, please return your homework on this problem sheet.

Category:
5/5 - (2 votes)

1
ECE 2029 Introduction to Digital Circuit Design
HOMEWORK # 3

Problems Score Instructor/TA’s Comments
1) /35
2) /20
3) /45
Total /100
TA’s/Instructor’s Signature: _________________________ Date: ___________________
Important (TIPS)
1. Show all the process work neatly, don’t just jump to answer. Partial credit may be given.
2. Read the problem carefully, don’t assume. Look for the simple, straightforward way to solve
the problem. Don’t overdo yourself.
3. To make the grading easier, please return your homework on this problem sheet.
4. If you need to use an extra piece of paper, please staple it on and number your solutions just
like below!
2
Problem 1 – 35 points total
We will design part of a set of logic circuits that tests numbers for divisibility for certain prime
numbers as part of an information encryption system. The binary number A is represented by a
four bit unsigned number: A = (a3; a2; a1; a0) where a0 is the least significant bit, etc. The circuit you
must design will have a single output, F, which must take on the value of 1 if A is divisible by 3 or 7
and zero otherwise, except when A = 0 (which is “technically” divisible by any number) for which
case we want F = 0.
(a) Give the truth table for F as a function of a3; a2; a1; a0. (5 pts)
F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
(b) Write out the canonical sum of Minterms expression for F. (5 pts)
F =
(c) Obtain a simplified expression for F using a Karnaugh Map. (5 pts)
Label essential prime implicants (EPI) with asterisk sign on the K-Map!
F =
4
(d) Draw the combinational logic circuit diagram that implements F. (5 pts)
(e) Write the Verilog code for the combinational logic circuit diagram that
implements F. (5 pts)
5
(f) Draw the combinational logic circuit diagram that implements F using NAND Gates only. (10 pts)
6
Problem 2 – 20 points total
For each of the following truth tables, use a Karnaugh map to produce a simplified sum of products expression.
The X’s in the tables indicate “don’t cares”. Be sure to show your Karnaugh map with clearly circled groups that correspond to your
sum of products solution. Please draw your final Karnaugh maps, clearly labeled and the resulting simplified logic expressions next to
them.
(a) Three Variable Map ( 5 pts)
X Y Z A
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
7
(b) Four Variable Map (5 pts) F = W X Y Z F 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1
8
(c) Three Variable Map (5 pts)
X Y Z C
0 0 0 0
0 0 1 1
0 1 0 X
0 1 1 1
1 0 0 0
1 0 1 X
1 1 0 0
1 1 1 X
C =
(d) Four Variable Map (5 pts)
D =
W X Y Z D
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 X
0 1 1 0 1
0 1 1 1 X
1 0 0 0 1
1 0 0 1 X
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 X
1 1 1 1 0
9
Problem 3 – 45 points total
For the function given:
F = (A + B + C) . (A + B’ + C) . (A + B’ + C’) . (A’ + B’ + C’)
(a) Produce a truth table that expresses F as a function of A, B, and C. (5 pts)
Note: You can do this on Logisim also.
(b) Use a Karnaugh map to produce a simplified sum of products form. (Show both
the Karnaugh map and Sum of Product expression.) (5 pts)
10
(c) Draw the circuit diagram of a NAND gate only implementation from your simplified sum of products (SOP)
expression. (15 pts)
11
(d) Use a Karnaugh map to produce a simplified product of sums (POS) form.
(Show both the K- map and simplified expression.)
(5 pts)
(e) Draw the circuit diagram of a NOR gate only implementation from your simplified product of sums (POS)
expression. (15 pts)

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